1. Field of the Invention
The invention relates to a structure of and a method for identifying the median reference voltage from among a group of reference voltages generated by bandgap reference circuits.
2. Description of Related Art
Bandgap reference circuits have been used to generate a reference voltage that remains substantially constant in the face of temperature variations. This is accomplished by adding a voltage that is "proportional to absolute temperature" (which has a positive temperature coefficient) to the negative temperature coefficient voltage of a bipolar diode (Vbe).
The critical factor in achieving a temperature insensitive reference voltage, is to add the correct amount of "proportional to temperature" voltage to the negative temperature coefficient base-emitter voltage (Vbe). Typically, the ratio of the positive temperature coefficient voltage to the negative temperature coefficient voltage is set by selecting proper resistor ratios and emitter area ratios of two bipolar diodes in the bandgap reference circuit.
Even with proper ratios selected, A few sources of error exist which cause the characteristics of the band gap reference voltage to deviate from that designed for. Such deviation is more apparent when identically designed multiple bandgap reference circuits are incorporated in the same chip or in multiple chips. Generally, the causes of variations between multiple bandgap reference voltages fall within one of two categories. One category includes those causes which result in a normal distribution, such as that shown in FIG. 1a. FIG. 1a depicts the typical bell-shaped distribution among five reference voltages VR.sub.1 -VR.sub.5, attributable to expected variations in the manufacturing process. These expected manufacturing variations cause mismatches among, for example, matching resistors, diodes and MOSFET devices.
The second category of causes is referred to as the "special causes". These causes are due to unexpected variations in the manufacturing process or other processes such as the assembly process. Among these causes are, particle defects, masking variations (misalignments), and photoresist tears, all of which can randomly cause the above-mentioned ratios to deviate from the target. The "special causes" result in reference voltages that significantly deviate from the "true" center of the distribution.
Combining these two categories of causes results in a distribution of reference voltages that looks like a normal distribution but with excessive population in the tails of the distribution, as shown in FIG. 1b. Any anomalistic or highly deviant reference voltages (such as VR.sub.1 or VR.sub.3) swings the average away from the "true" center of the distribution. This is especially true with smaller samples of reference voltages. These anomalistic or deviant units result in yield loss.
In the case of normal distribution (FIG. 1a), making the critical devices larger serves to reduce the impact of the category one causes by the square root of the area increase (i.e., increasing the area by four reduces the sigma of the distribution by two). But, such increases in devices result in larger silicon consumption and are also ineffective in reducing the impact of category two causes.
Trimming techniques at wafer level are used to improve the yield loss caused by the two categories of causes. Trimmable circuit components allow fine tuning of the reference voltage and the temperature characteristics of the bandgap circuit at wafer level. Two most popular trimming techniques are zener zapping and thin film laser trimming. Zener zapping does not work with modern fine line CMOS processes due to the use of barrier metal systems. Laser trimming of resistors requires the addition of thin film resistor process which is expensive, and the thin film process steps often conflict with fine line CMOS processes. Also, the process of laser trimming is itself slow and expensive.
Even though the wafer level trimming techniques help narrow the wide distribution due to the two categories of causes, the subsequent packaging process can cause the trimmed voltage distribution to spread widely, thereby causing yield loss at the package level. It is well known in the semiconductor art that the packaging process (whereby the wafer is cut via the die saw operation and each dice is attached to a leadframe and is subsequently encapsulated with a plastic molding compound) places a significant amount of stress on the dice. The stress results in sufficient changes in the characteristics of the circuit components to cause the reference voltage levels to shift, thereby widening the distribution and reducing performance and yield.
A solution to the wide distribution caused by the packaging process as well as the fabrication process is to provide trimming capability after packaging. But given the present state of technology, no simple and cost effective means of trimming packaged devices is available. Laser trimming of packaged devices requires ceramic packages with windows, which can be prohibitively costly. Electrical trimming of plastic packages requires the use of such process technologies as EEPROM (Electrically Erasable Programmable Read Only Memory), which is also costly and requires the integration of the complex EEPROM process.